An FET is a device in which regions called a source and a drain are provided in a semiconductor, each of the regions is provided with an electrode, potentials are supplied to the electrodes, and an electric field is applied to the semiconductor with the use of an electrode called a gate through an insulating film (called a gate insulating film) or a Schottky barrier so that the state of the semiconductor is controlled, whereby current flowing between the source and the drain is controlled. As the semiconductor, a Group 14 element such as silicon or germanium, a compound such as gallium arsenide, indium phosphide, gallium nitride, zinc sulfide, or cadmium telluride, or the like can be used.
In recent years, FETs in which an oxide such as zinc oxide or an indium gallium zinc oxide-based compound is used as a semiconductor have been reported (Patent Document 1 and Patent Document 2). In an FET including such an oxide semiconductor, relatively high mobility can be obtained, and such a material has a wide bandgap of 3 eV or more; therefore, application of the FET including an oxide semiconductor to displays, power devices, and the like is proposed.
The fact that the bandgap of such a material is 3 eV or more means that the material transmits visible light, for example; thus, in the case where the material is used in a display, even an FET portion can transmit light and the aperture ratio is expected to be improved.
Further, such a wide bandgap is common to silicon carbide, which is used in power devices; therefore, the oxide semiconductor is also expected to be applied to a power device.
Furthermore, a wide bandgap means few thermally excited carriers. For example, silicon has a bandgap of 1.1 eV at room temperature and thus thermally excited carriers exist therein at approximately 1011/cm3, while in a semiconductor with a bandgap of 3.2 eV, thermally excited carriers exist at approximately 10−7/cm3 according to calculation.
In the case of silicon, carriers generated by thermal excitation exist as described above even in silicon including no impurities, and thus the resistivity of the silicon cannot be 105 Ωcm or higher at room temperature. In contrast, in the case of the semiconductor with a bandgap of 3.2 eV, a resistivity of 1020 Ωcm or higher can be obtained in theory. When an FET is manufactured using such a semiconductor and its high resistivity in an off state (a state where the potential of a gate is the same as the potential of a source) is utilized, it is expected that electric charge can be retained semipermanently.
Meanwhile, there are few reports on an oxide semiconductor which includes zinc or indium in particular and has p-type conductivity. Therefore, an FET using a PN junction like an FET including silicon has not been reported. As disclosed in Patent Document 1 and Patent Document 2, a source and a drain are formed with the use of a conductor-semiconductor junction in which a conductor electrode or the like is in contact with an n-type or i-type oxide semiconductor (in this specification, an “i-type semiconductor” refers to a semiconductor having a carrier concentration of 1012/cm3 or lower) (such a junction is generally called a metal-semiconductor junction or a metal-insulator junction in academic books; in this specification, the term “conductor-semiconductor junction” is used for accurate interpretation of the term).